Alif Semiconductor /AE302F80F5582LE_CM55_HE_View /ETH /ETH_DMA_CH0_RX_CONTROL

Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: The current position in the list The position at which the Rx process was previously stopped When this bit is reset, the Rx DMA operation is stopped after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state.

0 (Val_0x0): Stop receive

1 (Val_0x1): Start receive

Receive Buffer Size Low RBSZ[13-0] is split into two fields RBSZ_13_Y and RBSZ_X_0. The RBSZ_X_0 is the lower field.

Receive Buffer Size High RBSZ[13-0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13-0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16KB. The buffer size is applicable to payload buffers when split headers are enabled. Note: The buffer size must be a multiple of 4, 8, or 16 depending on the data bus widths (32-bit, 64-bit, or 128-bit respectively). This is required even if the value of buffer address pointer is not aligned to data bus width. Hence the lower RBSZ_x_0 bits are read-only and the value is considered as all-zero. Thus the RBSZ_13_y indicates the buffer size in terms of locations (with the width same as bus-width).

Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. The user can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps:

1. Set the 8xPBL mode in the ETH_DMA_CH0_CONTROL register.
2. Set the RxPBL. Note: The maximum value of RxPBL must be less than or equal to half the Rx Queue size in terms of beats. This is required so that the Rx Queue has space to store at least another Rx PBL worth of data while the Rx DMA is transferring a block of data. For example, the total locations in Rx Queue of size 512 bytes is 64, so RxPBL and 8xPBL needs to be programmed to less than or equal to 32.

Rx Packet Flush. When this bit is set to 1, then the ETH module automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel, when it is stopped. When this bit remains set and the DMA is re-started by the software driver, the packets residing in the Rx Queues that were received when this Rx DMA was stopped, get flushed out. The packets that are received by the MAC after the Rx DMA is re-started are routed to the Rx DMA. The flushing happens on the Read side of the Rx Queue. When this bit is set to 0, the ETH module does not flush the packet in the Rx Queue destined to this Rx DMA Channel when it is STOP state. This may in turn cause head-of-line blocking in the corresponding RxQueue.

0 (Val_0x0): Rx packet flush is disabled

1 (Val_0x1): Rx packet flush is enabled